Yesterday was a very important day for AMD, and there is no doubt that Zen 4 architecture was one of the great protagonists. Yes, it is true that the Ryzen 6000 APUs generated a lot of interest, and it is understandable, since they are the first solutions that will reach the general consumer market equipped with integrated Radeon RDNA 2 GPUs, but the highlight was in that architecture, and we are going to see why.
I do not speak without reason. Zen 4 will be the architecture that will define the future of AMD in the medium and long term, and will be the basis for the upcoming Ryzen 7000 processors, as well as the next-generation Threadripper and EPYC. Its importance is beyond any doubt, and it is that, as we have just seen, Zen 4 is going to be the pillar on which AMD will build its next ecosystem of high-performance general consumption processors, as well as HEDT and server chips.
During this year’s CES, AMD confirmed some important details about Zen 4, and we have also been able to see some leaks that, in the end, have left us a very interesting base that I wanted to group, and substantiate, in this article. First of all, I remind you that the launch of the first general consumer processors based on Zen 4 will not occur until second half of this year, and that therefore there is still room for changes to take place, although in any case these should be minor.
Zen 4: The chiplet will continue to be the key piece
AMD introduced the chiplet concept with the Zen 2 architecture, used in the Ryzen 3000 series processors. This architecture was characterized by outsource all I / O elements, which greatly simplified the design of these new processors. Each chiplet had 8 cores and 32MB L3 cache (each quad core block could access 16MB), and was built on TSMC’s 7nm node, while the I / O chip was built on 12nm process .
Zen 3 kept that approach, but improved chiplet design and unified L3 cache, so that the 8 cores of the chiplet could access the 32 MB of L3 cache. This, together with the other improvements, allowed a notable increase in the CPI, and made it possible for AMD to finally outperform Intel in single-threaded performance even though its CPUs continued to run at slightly lower speeds. With Alder Lake-S the situation changed completely, as we already told you at the time, since Intel managed to regain the crown of single-wire performance.
Well, Zen 4 is going to keep the chiplet concept as we saw it in Zen 3, but with a very important change, which is that said architecture will double the number of cores per chiplet, which will go from 8 cores to 16 cores. This will be possible thanks to the integration of 3D stacked L3 cache, which will reduce the space it will occupy on the chip, and also thanks to the use of the new TSMC 5nm fabrication process, which will reduce the size of the transistors, and therefore the space that each processor core will occupy.
Starting from that base, we have that a single chiplet based on Zen 4 would have 16 cores, could handle up to 32 threads thanks to SMT technology and would add up, in total, 64MB L3 cache stacked in 3D which, in theory, should be accessible by all cores (otherwise it would be a step backwards by AMD). For its part, the L2 cache memory would amount to a total of 8 MB, 512 KB per core, and the I / O chip would be manufactured in 6 nm process.
AMD has already confirmed that with Zen 4 it will increase the maximum number of cores of its new generation EPYC processors, so the concept of chiplet with 16 cores and 32 threads It has all the sense of the world. However, we must bear in mind that some minor technical details could differ, as we are working with unofficial information that comes from leaks and therefore is not fully valid.
High-performance cores and efficient cores: Zen 4 would take a very peculiar approach
The hybrid design that Intel adopted with Alder Lake-S did not leave anyone indifferent, and in the end it turned out to be a success. That design allowed the chip giant to build processors with higher multi-threaded performance without having to forgo high single-threaded performance, and without space on the chip being a problemAs in the end, four high-efficiency cores occupy almost the same size as a high-performance chip.
AMD won’t have a chip space issue with Zen 4, thanks to the use of the stacked cache in 3D and the jump to the 5nm node, but you will have to solve a very important issue: the consumption and the heat generated. This raises an important question, How do you integrate 16 cores into a chiplet without compromising those values? A solution would be to reduce the working frequencies, but this could greatly affect the overall performance of the chip, especially in environments and applications where single-wire performance is more prime.
The answer lies, according to an interesting leak, in the use of a high-performance core block and another high-efficiency core block. It is a very simple idea, AMD could use, in a chiplet, 8 high-performance Zen 4 cores that would work with a normal TDP and another block of 8 Zen 4 cores that they would have a TDP limited to 30 watts. This would make it possible to set a maximum TDP of 170 watts, and allow AMD to raise the bar for multi-threaded performance.
I know what you are thinking, and how would those cores work, would it take a conductor to order and assign each workload, as with Alder Lake-S? Well in theory no, since AMD would start from a very simple concept: all the work would always go to the cores with a normal TDP, known as “priority”, and only when these were saturated would the low-power cores come into operation.
If we move all this to the general consumer market, we see that the successor to the Ryzen 9 5950X, a hypothetical Ryzen 9 7950X, should be based on two Zen 4 chiplets, which would leave us a total of 32 cores and 64 threadsplus 128MB of 3D stacked L3 cache. Its TDP would be 170 watts, as we have said. The improvement in multi-thread performance that this would bring would be huge, but the jump in single-thread performance is not going to be far behind. According to various sources, a low-power Zen 4 core is capable of slightly outperforming a Zen 3 core, so a standard Zen 4 core will be way above a Zen 3 core.
Zen 4 will use a state-of-the-art platform, and will tear down a major barrier
We have already seen the most important keys of Zen 4 at the architectural level, so we are ready to delve into other questions. The first is going to be the platform, and that is, with the launch of the Ryzen 7000, AMD will introduce a totally new socket, and it will make the leap from the current pin-based CPU (PGA) connection system to one based on contact arrays (LGA). This will mean the end of the AM4 socket, and the beginning of a new stage.
The new AMD socket is known as AM5 (LGA1718), and it will be accompanied by the new 600 series chipsets. In previous information we had seen that it could be limited to DDR4 memory, but now everything seems to indicate that it will be an up-to-date platform, and which will therefore offer support for DDR5, and also for the new PCIE Gen5 standard. DDR5 memory support was confirmed by AMD itself, who demonstrated Halo Infinite at CES 2022 on a computer based on a Ryzen 7000 (Zen 4) prototype, an AMD reference design motherboard, 32GB of dual channel 4800MHz DDR5 memory, and a GeForce RTX 3080.
That demonstration also left us a very interesting piece of information, and that is that the Ryzen 7000 CPU they used it ran at 5 GHz with all its cores active. Indeed, it was not a specific peak in turbo mode with an active thread, but a stable turbo mode with a realistic and wide workload. This data is very important because it confirms that AMD has managed to overcome one of the most important shortcomings of multi-chip CPU designs, the maximum peak operating frequency.
Those of you who read us daily will remember that AMD an unnecessary problem was created by obsessing over 5 GHz, a topic that we already touched on at the time in this article, and that is why it is especially worth mentioning that it has managed to overcome that barrier with Zen 4. Also bear in mind that if that Ryzen 7000 can operate at 5 GHz with all active cores , too You will be able to exceed that number if you only work with one or two active cores.
We have one last detail that I wanted to leave for last because it is one of the ones that attracts me the most, and that is that all Ryzen 7000 processors based on Zen 4 will come, in theory, with an integrated GPU based on RDNA2 architecture. Yes, you have read correctly, all, which means that these will offer a very interesting value. This jump by AMD has a very simple explanation, on the one hand is the answer to the integration of the Xe Gen12 GPUs in the Intel Alder Lake-SOn the other hand, it is a movement that now, with the adoption of DDR5, makes sense and is perfectly viable.
In case someone has gotten lost, I remind you that it made no sense to make the leap to an integrated GPU based on RDNA 2 because that increase in power, derived from that new architecture, was going to be weighed down by the lower bandwidth offered by the DDR4 memory vs. DDR5. You already know that an integrated GPU uses system RAM as graphics memory, and that is why the jump to DDR5 was so necessary.